Group III-V semiconductor devices are semiconductor devices formed from compounds with at least one group III element (IUPAC group 13) and at least one group V element (IUPAC group 15). Group III elements include boron, aluminum, gallium, indium, and thallium. Group V elements include nitrogen, phosphorus, arsenic, antimony, and bismuth. Currently, nitrogen is the most commonly used group V element in semiconductor devices.
Group III-V semiconductor compounds, such as gallium nitride (GaN) and its related alloys, are known to be well suited for the formation of optical devices. The large bandgap and high electron saturation velocity of the group III-V semiconductor compounds also make them excellent candidates for applications in high temperature and high-speed power electronics. For example, GaN is frequently used in forming diodes and transistors including light-emitting diodes (LEDs), laser diodes, UV photodetectors. GaN devices are particularly suited for use in power devices that are required to provide high current capability, such as radiofrequency (RF) amplification, high voltage power amplification, and optoelectronics.
However, it is difficult to obtain GaN bulk crystals due to the high equilibrium pressure of nitrogen at typical growth temperatures. To form GaN devices, GaN is commonly deposited epitaxially on silicon having a (111) crystal orientation. However, silicon (111) substrates suffer from interface traps and are not suitable for the formation of complementary metal oxide semiconductor (CMOS) devices. Therefore, GaN device fabrication and CMOS device fabrication are not commonly integrated over a common substrate.
To form integrated circuits with GaN devices and CMOS devices, CMOS devices are typically formed on a first substrate, such as a silicon (100) substrate and GaN devices are formed on a second substrate, such as a silicon (111) substrate. The GaN devices and CMOS devices are then connected together using various approaches including assembling the GaN and CMOS devices in separate semiconductor packages and connecting them on a printed circuit board, assembling the GaN and CMOS devices into a single package and connecting them via the package conductive materials and/or wire bonds, or using layer transfer techniques to physically couple the CMOS devices in their substrate and the GaN devices in their substrate. In the latter approach, electrical interconnects between GaN devices and CMOS devices can be formed using back-end-of-line (BEOL) semiconductor processes, such as the formation of multiple levels of dielectric layers and metal interconnection layers. Such interconnections between integrated GaN and CMOS devices have encountered issues such as poor adhesion of the metal layers. Further, current methods for electrically connecting GaN devices and CMOS devices are time-consuming and expensive.
Accordingly, it is desirable to provide an improved method for fabricating integrated circuits using layer transfer methods to physically couple III-V devices and CMOS devices. Also, it is desirable to provide an improved method for fabricating electrical interconnects to couple CMOS devices and III-V devices. It is further desirable to provide integrated circuits having III-V devices and CMOS devices with electrical interconnects therebetween. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.